55 #ifndef FOXBMS__MXM_41B_REGISTER_MAP_H_
56 #define FOXBMS__MXM_41B_REGISTER_MAP_H_
84 #define MXM_BUF_CLR_TX_BUF ((MXM_41B_BUF_CMD_t)0x20u)
89 #define MXM_BUF_RD_MSG ((MXM_41B_BUF_CMD_t)0x91u)
94 #define MXM_BUF_RD_NXT_MSG ((MXM_41B_BUF_CMD_t)0x93u)
99 #define MXM_BUF_WR_NXT_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xB0u)
104 #define MXM_BUF_WR_NXT_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xB2u)
109 #define MXM_BUF_WR_NXT_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xB4u)
114 #define MXM_BUF_WR_NXT_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xB6u)
119 #define MXM_BUF_WR_NXT_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xB8u)
124 #define MXM_BUF_WR_NXT_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xBAu)
129 #define MXM_BUF_WR_NXT_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xBCu)
134 #define MXM_BUF_WR_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xC0u)
139 #define MXM_BUF_WR_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xC2u)
144 #define MXM_BUF_WR_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xC4u)
149 #define MXM_BUF_WR_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xC6u)
154 #define MXM_BUF_WR_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xC8u)
159 #define MXM_BUF_WR_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xCAu)
164 #define MXM_BUF_WR_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xCCu)
169 #define MXM_BUF_RD_LD_Q_0 ((MXM_41B_BUF_CMD_t)0xC1u)
174 #define MXM_BUF_RD_LD_Q_1 ((MXM_41B_BUF_CMD_t)0xC3u)
179 #define MXM_BUF_RD_LD_Q_2 ((MXM_41B_BUF_CMD_t)0xC5u)
184 #define MXM_BUF_RD_LD_Q_3 ((MXM_41B_BUF_CMD_t)0xC7u)
189 #define MXM_BUF_RD_LD_Q_4 ((MXM_41B_BUF_CMD_t)0xC9u)
194 #define MXM_BUF_RD_LD_Q_5 ((MXM_41B_BUF_CMD_t)0xCBu)
199 #define MXM_BUF_RD_LD_Q_6 ((MXM_41B_BUF_CMD_t)0xCDu)
204 #define MXM_BUF_CLR_RX_BUF ((MXM_41B_BUF_CMD_t)0xE0u)
209 #define MXM_REG_RX_STATUS_R ((MXM_41B_REG_ADD_t)0x01u)
214 #define MXM_REG_TX_STATUS_R ((MXM_41B_REG_ADD_t)0x03u)
219 #define MXM_REG_RX_INTERRUPT_ENABLE_R ((MXM_41B_REG_ADD_t)0x05u)
224 #define MXM_REG_RX_INTERRUPT_ENABLE_W ((MXM_41B_REG_ADD_t)0x04u)
229 #define MXM_REG_TX_INTERRUPT_ENABLE_R ((MXM_41B_REG_ADD_t)0x07u)
234 #define MXM_REG_TX_INTERRUPT_ENABLE_W ((MXM_41B_REG_ADD_t)0x06u)
239 #define MXM_REG_RX_INTERRUPT_FLAGS_R ((MXM_41B_REG_ADD_t)0x09u)
244 #define MXM_REG_RX_INTERRUPT_FLAGS_W ((MXM_41B_REG_ADD_t)0x08u)
249 #define MXM_REG_TX_INTERRUPT_FLAGS_R ((MXM_41B_REG_ADD_t)0x0Bu)
254 #define MXM_REG_TX_INTERRUPT_FLAGS_W ((MXM_41B_REG_ADD_t)0x0Au)
259 #define MXM_REG_CONFIGURATION_1_R ((MXM_41B_REG_ADD_t)0x0Du)
264 #define MXM_REG_CONFIGURATION_1_W ((MXM_41B_REG_ADD_t)0x0Cu)
269 #define MXM_REG_CONFIGURATION_2_R ((MXM_41B_REG_ADD_t)0x0Fu)
274 #define MXM_REG_CONFIGURATION_2_W ((MXM_41B_REG_ADD_t)0x0Eu)
279 #define MXM_REG_CONFIGURATION_3_R ((MXM_41B_REG_ADD_t)0x11u)
284 #define MXM_REG_CONFIGURATION_3_W ((MXM_41B_REG_ADD_t)0x10u)
289 #define MXM_REG_FMEA_R ((MXM_41B_REG_ADD_t)0x13u)
294 #define MXM_REG_MODEL_R ((MXM_41B_REG_ADD_t)0x15u)
299 #define MXM_REG_VERSION_R ((MXM_41B_REG_ADD_t)0x17u)
304 #define MXM_REG_RX_BYTE_R ((MXM_41B_REG_ADD_t)0x19u)
309 #define MXM_REG_RX_SPACE_R ((MXM_41B_REG_ADD_t)0x1Bu)
314 #define MXM_REG_TX_QUEUE_SELECTS_R ((MXM_41B_REG_ADD_t)0x95u)
319 #define MXM_REG_RX_READ_POINTER_R ((MXM_41B_REG_ADD_t)0x97u)
324 #define MXM_REG_RX_WRITE_POINTER_R ((MXM_41B_REG_ADD_t)0x99u)
329 #define MXM_REG_RX_NEXT_MESSAGE_R ((MXM_41B_REG_ADD_t)0x9Bu)
338 #ifdef UNITY_UNIT_TEST
uint8_t MXM_41B_BUF_CMD_t
Type for MAX17841B buffer transaction commands.
uint8_t MXM_41B_REG_ADD_t
MAX17841B register addresses.